搜索资源列表
maxshiyan
- 大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法器,数字钟,数码显示,74ls138,8,4位计数器,d,rs触发器,加法器,交通灯等,此原码基于长江大学可编程器件实验箱,如要运行在其他平台上需要重新定义管脚-University VHDL language experiment Daquan, based on the max-plus2 platform within 8-3 decoder, 8 Adder, digital clock, digital d
clockyzl
- vhdl语言,实现数字钟的设计,用component实现-vhdl languages, digital clock design, component achievement
dzzh
- eda课程设计:数字钟--vhdl语言全部源代码
MyClockTest
- 这是我电子线路测试的作业,在FPGA板上实现数字钟,(Max2环境)采用VHDL语言编写,非常适合初学者。具备24小时计时,校时,低高音整点报时,定时和多重功能选择的功能。-This is my test of electronic circuits operating at the FPGA board digital clock (Max2 Environment) using VHDL language, very suitable for beginners. 24-hour time,
dig_clk_lcd
- 数字钟的实现,由LCD动态显示,VHDL语言实现-the realization by the dynamic display LCD, VHDL
shuzizhong
- 介绍了用VHDL设计数字钟的相关知识,是学习VHDL的经典例子.
eda
- 南京理工大学EDA实验多功能数字钟+闹钟+dds+am调幅。-Nanjing University of EDA test multifunction digital clock+ alarm+ dds+ am AM.
vhdl-digital
- VHD L数字钟 设计源码 包括 设计思想 设计模块 -VHD L source, including digital clock design design design module
VHDL-digital-clock-
- VHDL编写的数字钟,采用元件例化的方法,可实现调秒 调分 调时 报时 闹铃的功能 开发板使用的是EP3C16Q240C8-Digital clock written in VHDL, using the example of the way components can be adjusted to achieve sub-second tone when the alarm tone Times feature development board using EP3C16Q240C8
EDA-experiments-based-on-VHDL
- 上传的文件包括E有关EDA实验的程序,比如FIFO,秒表,数字钟,七段数码管,状态机检测序列-The files uploaded contain some source code of EDA experiments based on VHDL, such as FIFO, digital clock, stop watch, digital tubes and sequential detector.
shuzhizhong(vhdl)
- 数字钟设计 计时计数器用24进制计时电路; 可手动校时,能分别进行时、分的校正; 整点报时; 选做:可设置闹时功能,当计时计到预定时间时,扬声器发出闹铃信号,闹铃时间为4s,并可提前终止闹铃。-Digital clock design
Chess-chess-clock-by-VHDL
- 国际象棋棋钟程序。实现棋钟基本功能,及下棋步数计数。-Chess chess clock program. Chess clock to achieve the basic functions, and chess step counting.
VHDL-clock
- 用VHDL写的数字钟程序,能够实现显示时分秒,时间可以调节,还能设定闹钟-Written in VHDL,the digital clock procedures can display every minute, the time can be adjusted, but also to set the alarm
VHDL-Multi-fuction-Clock
- 设计一个多功能数字钟,要求显示格式为小时-分钟-秒钟,整点报时,报时时间为10 秒,即从整点前10 秒钟开始进行报时提示,喇叭开始发声,直到过整点时,在整点前5 秒LED 开始闪烁,过整点后,停止闪烁。系统时钟选择时钟模块的10KHz,要得到1Hz 时钟信号,必须对系统时钟进行10,000次分频。调整时间的的按键用按键模块的S1 和S2,S1 调节小时,每按下一次,小时增加一个小时,S2 调整分钟,每按下一次,分钟增加一分钟。另外用S8 按键作为系统时钟复位,复位后全部显示00-00-00。-T
shuzizhong
- 数字电子钟设计,包括时、分、秒模块,文件中包括使用VHDL语言编写源码以及原理图(时、分、秒模块)(Digital clock source as well as schematic)
timer_24
- 实现数字钟功能,带有按键调整时间,定时闹钟功能(Digital clock function, with timing, alarm clock function)
clock
- 数字钟可以实现整点响铃,预置数,十二小时24小时切换(Digital clock can achieve the whole point of the bell)
shuzizhong
- 基于vhdl语言的多功能数字钟设计,硬件调试成功(Design of multi-function digital clock based on vhdl)
clock
- 用VHDL完成的数字钟设计。可选24h与12h两种时制,运用到按键消抖。(The digital clock is designed with VHDL. Optional 24h and 12h two kinds of time system, apply to the button to shake.)
szz
- 数字钟,24小时时制,每隔一分钟报时,每次两秒钟(A digital clock, ring lasts for two seconds per minute)